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[/] [rise/] [trunk/] [vhdl/] [id_stage.vhd] - Rev 149

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Rev Log message Author Age Path
148 New directory structure. root 5600d 16h /rise/trunk/vhdl/id_stage.vhd
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6383d 00h /rise/trunk/vhdl/id_stage.vhd
100 - Signal clear_in was missing in sensitivity list. cwalter 6386d 05h /rise/trunk/vhdl/id_stage.vhd
92 Added logic for inserting a nop instruction when the pipeline is cleared. jlechner 6386d 07h /rise/trunk/vhdl/id_stage.vhd
73 - Fixed bug where immediate value for LD_IMM_HB was placed in
the upper 8bits. This is done by the execute stage.		 cwalter 6386d 12h /rise/trunk/vhdl/id_stage.vhd
72 Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation

Added call to conversion function where a std_logic_vector is assigned to a opcode signal or a condition signal.		 jlechner 6386d 22h /rise/trunk/vhdl/id_stage.vhd
63 - Added missing signal stall_out_int to sensitivity list.
- LR register now locked if opcode is JUMP.		 cwalter 6387d 00h /rise/trunk/vhdl/id_stage.vhd
59 - We don't want to lock registers the next cycle when we have stalled
the previous stages.
- Load opcodes also need to lock registers.		 cwalter 6387d 02h /rise/trunk/vhdl/id_stage.vhd
51 - stall_out logic has moved to synchronous process. cwalter 6387d 05h /rise/trunk/vhdl/id_stage.vhd
32 - When this stage asserts stall_out it must clear the input for the next
stage.
- Fixed process sensitivity list.		 cwalter 6388d 03h /rise/trunk/vhdl/id_stage.vhd
20 - Fixed bug where SR fetch code locked wrong register. cwalter 6392d 01h /rise/trunk/vhdl/id_stage.vhd
15 - Added second register locking port reg_lock1.
- Added function to check if the instruction modifies the SR register.
- Fetch of SR now checks if the SR is modified and if yes the SR register
is marked as locked.
- Stall signal for pipeline is now generated correctly.
- Stall input is now checked. If asserted the current output values are hold
until the stall signal is deasserted.		 cwalter 6395d 01h /rise/trunk/vhdl/id_stage.vhd
11 - Added checks to test if a register has been locked. If it is locked and
used in the decoded instruction the stall_out signal is asserted.
- Added missing signals to process sensitivity list.
- Fixed bug in rY decoding where the value of rZ was used.
- Implemented opcode_modifies_rx.		 cwalter 6397d 23h /rise/trunk/vhdl/id_stage.vhd
9 - added support for immediate value decoding.
- opcode extender now works correctly for load immediate. needed special
handling for the high byte bit.
- conditional decoder needed special handling for high byte bit.		 cwalter 6400d 02h /rise/trunk/vhdl/id_stage.vhd
6 - applied VHDL source code indenter. cwalter 6418d 23h /rise/trunk/vhdl/id_stage.vhd
4 - added decode for rX, rY, rZ.
- added decode for opcodes.		 cwalter 6418d 23h /rise/trunk/vhdl/id_stage.vhd
2 Initial commit of project jlechner 6425d 02h /rise/trunk/vhdl/id_stage.vhd

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