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[/] [rise/] [trunk/] [vhdl/] [if_stage.vhd] - Rev 149

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Rev Log message Author Age Path
148 New directory structure. root 5600d 16h /rise/trunk/vhdl/if_stage.vhd
144 - IF stage now uses autogenerated VHDL files. cwalter 6375d 02h /rise/trunk/vhdl/if_stage.vhd
134 Added second test program for testing uart. jlechner 6376d 00h /rise/trunk/vhdl/if_stage.vhd
132 Added test program for testing uart. jlechner 6376d 02h /rise/trunk/vhdl/if_stage.vhd
107 - Added new example for memory testing. cwalter 6383d 23h /rise/trunk/vhdl/if_stage.vhd
93 Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result. jlechner 6386d 06h /rise/trunk/vhdl/if_stage.vhd
86 - Added new example for a more complex loop. cwalter 6386d 07h /rise/trunk/vhdl/if_stage.vhd
85 Removed PC reset on clear_in signal. Clear_in only comes together with a branch, so it is sufficient
branch immediately.		 jlechner 6386d 10h /rise/trunk/vhdl/if_stage.vhd
84 - PC value was wrong. cwalter 6386d 10h /rise/trunk/vhdl/if_stage.vhd
78 Added stall_in to sensitivity list. jlechner 6386d 10h /rise/trunk/vhdl/if_stage.vhd
71 Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation		 jlechner 6386d 21h /rise/trunk/vhdl/if_stage.vhd
50 - Added assembler example.
- Added logic for stall_in. pc_next must not be updated on stall.		 cwalter 6387d 05h /rise/trunk/vhdl/if_stage.vhd
45 - Fixed latch for pc_next. cwalter 6388d 01h /rise/trunk/vhdl/if_stage.vhd
33 - Fixed process sensitivity list. cwalter 6388d 02h /rise/trunk/vhdl/if_stage.vhd
29 - Initial version of IF stage with dummy instructions. cwalter 6388d 04h /rise/trunk/vhdl/if_stage.vhd
2 Initial commit of project jlechner 6425d 02h /rise/trunk/vhdl/if_stage.vhd

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