URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [memctrl.vhd] - Rev 151

Rev	Log message	Author	Age	Path
151	Started to include generic VHDL description of memories.	jlechner	5358d 23h	/rise/trunk/vhdl/memctrl.vhd
148	New directory structure.	root	5695d 10h	/rise/trunk/vhdl/dmem.vhd
135	uart_address_0 was a latch -> changed	ustadler	6470d 19h	/rise/trunk/vhdl/dmem.vhd
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6470d 21h	/rise/trunk/vhdl/dmem.vhd
125	Fixed vhdl bugs	trinklhar	6471d 03h	/rise/trunk/vhdl/dmem.vhd
120	Added UART module to memory entity	trinklhar	6471d 05h	/rise/trunk/vhdl/dmem.vhd
98	- Applied indenting tool.	cwalter	6480d 23h	/rise/trunk/vhdl/dmem.vhd
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6481d 16h	/rise/trunk/vhdl/dmem.vhd
60	- Applied indenting tool.	cwalter	6481d 20h	/rise/trunk/vhdl/dmem.vhd
37	Applied VHDL indent.	jlechner	6482d 20h	/rise/trunk/vhdl/dmem.vhd
23	4k Data Memory for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6485d 16h	/rise/trunk/vhdl/dmem.vhd
2	Initial commit of project	jlechner	6519d 20h	/rise/trunk/vhdl/dmem.vhd