URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [rise.vhd] - Rev 150

Rev	Log message	Author	Age	Path
148	New directory structure.	root	5719d 03h	/rise/trunk/vhdl/rise.vhd
124	Assigned UART signals to ports on top-level entity	trinklhar	6494d 20h	/rise/trunk/vhdl/rise.vhd
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6504d 17h	/rise/trunk/vhdl/rise.vhd
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6505d 08h	/rise/trunk/vhdl/rise.vhd
58	- lr_enable signal in component wb_state should have direction out.	cwalter	6505d 14h	/rise/trunk/vhdl/rise.vhd
39	- Added wr_enable signals for imem and dmem - Changed signals for register lock unit (this concerns id-stage and write-back-stage)	jlechner	6506d 13h	/rise/trunk/vhdl/rise.vhd
27	Added new register write enable signals to component instantiation of register_file and wb_stage.	jlechner	6508d 09h	/rise/trunk/vhdl/rise.vhd
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6513d 12h	/rise/trunk/vhdl/rise.vhd
2	Initial commit of project	jlechner	6543d 13h	/rise/trunk/vhdl/rise.vhd