URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [tb_id_stage_unit.vhd] - Rev 148

Rev	Log message	Author	Age	Path
148	New directory structure.	root	5586d 15h	/rise/trunk/vhdl/tb_id_stage_unit.vhd
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6372d 21h	/rise/trunk/vhdl/tb_id_stage_unit.vhd
17	- Added new tests for pipeline stall signal. - Added tests for register locking. - Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.	cwalter	6381d 00h	/rise/trunk/vhdl/tb_id_stage_unit.vhd
13	- Testbench now implements a simple register file. - Added new tests for OPCODE_LD_DISP, OPCODE_LD_DISP_MS OPCODE_LD_REG.	cwalter	6383d 22h	/rise/trunk/vhdl/tb_id_stage_unit.vhd
10	- added testbench for load immediate and load immediate with high byte.	cwalter	6386d 01h	/rise/trunk/vhdl/tb_id_stage_unit.vhd
7	- initial version of instruction decode stage testbench.	cwalter	6404d 22h	/rise/trunk/vhdl/tb_id_stage_unit.vhd