URL https://opencores.org/ocsvn/rs232_with_buffer_and_wb/rs232_with_buffer_and_wb/trunk

Subversion Repositories rs232_with_buffer_and_wb

[/] [rs232_with_buffer_and_wb/] [trunk/] [rtl/] [uart_tx.vhd] - Rev 49

Rev	Log message	Author	Age	Path
38	Moved RTL code to RTL folder	TobiasJ	4245d 05h	/rs232_with_buffer_and_wb/trunk/rtl/uart_tx.vhd
29	tested to work	TobiasJ	4248d 03h	/rs232_with_buffer_and_wb/trunk/uart_tx.vhd
19	renamed the file	TobiasJ	4252d 08h	/rs232_with_buffer_and_wb/trunk/uart_tx.vhd
13	Fixed a error in enable_register, which made it possible to commense a transmittion and provide wrong timing at will	TobiasJ	4257d 02h	/rs232_with_buffer_and_wb/trunk/tx.vhd
9	Primilary tests shows it is working. The issue with the second and following starts bit being to short has been solved. no new issues has been found	TobiasJ	4259d 03h	/rs232_with_buffer_and_wb/trunk/tx.vhd
5	Triede to clearly seperate combinational logic with register logic, to have more control. Problem after first word is transmitted, the counter counts one to many going into idle mode, therby reducing the count for the secound and following start bits	TobiasJ	4259d 05h	/rs232_with_buffer_and_wb/trunk/tx.vhd
4	Testing SVN and SVN program	TobiasJ	4259d 05h	/rs232_with_buffer_and_wb/trunk/tx.vhd
3	The transmission part of the project	TobiasJ	4259d 05h	/rs232_with_buffer_and_wb/trunk/tx.vhd