URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsl.v] - Rev 25

Rev	Log message	Author	Age	Path
23	- added subtract immediate from sp - added stack relative addressing mode - added move positive, move negative instructions - fix: TSA instruction	robfinch	3937d 13h	/rtf65002/trunk/rtl/verilog/byte_jsl.v
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	3939d 08h	/rtf65002/trunk/rtl/verilog/byte_jsl.v
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	3942d 13h	/rtf65002/trunk/rtl/verilog/byte_jsl.v
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	3945d 18h	/rtf65002/trunk/rtl/verilog/byte_jsl.v
5	setting up project	robfinch	3949d 02h	/rtf65002/trunk/rtl/verilog/byte_jsl.v