URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_plp.v] - Rev 31

Rev	Log message	Author	Age	Path
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	4073d 09h	/rtf65002/trunk/rtl/verilog/byte_plp.v
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	4076d 13h	/rtf65002/trunk/rtl/verilog/byte_plp.v
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	4079d 18h	/rtf65002/trunk/rtl/verilog/byte_plp.v
5	setting up project	robfinch	4083d 02h	/rtf65002/trunk/rtl/verilog/byte_plp.v