URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [ifetch.v] - Rev 41

Rev	Log message	Author	Age	Path
38	- updated to support the 65c816 opcodes	robfinch	3838d 14h	/rtf65002/trunk/rtl/verilog/ifetch.v
36	- missing TRB/TSB instructions in 32 bit mode added	robfinch	3987d 09h	/rtf65002/trunk/rtl/verilog/ifetch.v
35	- several bug fixes - mul,mod,div immediates mode than 8 bits - page two opcode fix on cache miss - setting upper pc bits in emulation mode (store)	robfinch	4034d 01h	/rtf65002/trunk/rtl/verilog/ifetch.v
32	- many changes - new instructions - code reorganization	robfinch	4044d 15h	/rtf65002/trunk/rtl/verilog/ifetch.v
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	4054d 13h	/rtf65002/trunk/rtl/verilog/ifetch.v
25	- add EXEC and ATNI instructions - fix store byte zero page indexed - fix break instruction	robfinch	4061d 15h	/rtf65002/trunk/rtl/verilog/ifetch.v
23	- added subtract immediate from sp - added stack relative addressing mode - added move positive, move negative instructions - fix: TSA instruction	robfinch	4067d 13h	/rtf65002/trunk/rtl/verilog/ifetch.v
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	4070d 14h	/rtf65002/trunk/rtl/verilog/ifetch.v