URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_pcinc.v] - Rev 37

Rev	Log message	Author	Age	Path
36	- missing TRB/TSB instructions in 32 bit mode added	robfinch	3883d 11h	/rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v
35	- several bug fixes - mul,mod,div immediates mode than 8 bits - page two opcode fix on cache miss - setting upper pc bits in emulation mode (store)	robfinch	3930d 04h	/rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v
32	- many changes - new instructions - code reorganization	robfinch	3940d 18h	/rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	3950d 16h	/rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v