OpenCores
URL https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk

Subversion Repositories rtfsimpleuart

[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [rtfSimpleUartRx.v] - Rev 13

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
13 - updated license notice robfinch 4013d 09h /rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartRx.v
12 +BaudX8 mode
!start frame detector - checks 1->0 transition
!frame complectness - frame completes right after center of a frame bit, allows more difference of sender and reciever baud
AlexRayne 4013d 15h /rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartRx.v
5 robfinch 4809d 15h /rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartRx.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.