URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Rev 54

Rev	Log message	Author	Age	Path
51	Latest RTL changes, adding 20 cycles/instruction to CPU	dgisselq	2746d 15h	/s6soc/trunk/rtl/altbusmaster.v
46	Added missing files from the 8b branch, deleted unneeded files	dgisselq	2765d 16h	/s6soc/trunk/rtl/altbusmaster.v
32	Removed an undefined value from o_lcd[2] setting.	dgisselq	3064d 05h	/s6soc/trunk/rtl/altbusmaster.v
25	Converted timer B to be a non-reloadable watchdog timer.	dgisselq	3068d 16h	/s6soc/trunk/rtl/altbusmaster.v
13	Fixed a nasty parameter problem between toplevel and txuart. The UART transmitter now both works (again), and properly generates the required interrupts. This also finishes the fixes to the alternate toplevel file, alttop.v, that should've been fixed in the last release.	dgisselq	3078d 09h	/s6soc/trunk/rtl/altbusmaster.v
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	3080d 05h	/s6soc/trunk/rtl/altbusmaster.v
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	3085d 05h	/s6soc/trunk/rtl/altbusmaster.v
5	These two are my first attempt(s) at a secondary project file, one that can run as an alternate to the main file but that gives more access to the hardware, such as programming access to the flash.	dgisselq	3106d 15h	/s6soc/trunk/rtl/altbusmaster.v