URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [alttop.v] - Rev 54

Rev	Log message	Author	Age	Path
51	Latest RTL changes, adding 20 cycles/instruction to CPU	dgisselq	2709d 16h	/s6soc/trunk/rtl/alttop.v
46	Added missing files from the 8b branch, deleted unneeded files	dgisselq	2728d 17h	/s6soc/trunk/rtl/alttop.v
13	Fixed a nasty parameter problem between toplevel and txuart. The UART transmitter now both works (again), and properly generates the required interrupts. This also finishes the fixes to the alternate toplevel file, alttop.v, that should've been fixed in the last release.	dgisselq	3041d 10h	/s6soc/trunk/rtl/alttop.v
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	3048d 06h	/s6soc/trunk/rtl/alttop.v
5	These two are my first attempt(s) at a secondary project file, one that can run as an alternate to the main file but that gives more access to the hardware, such as programming access to the flash.	dgisselq	3069d 16h	/s6soc/trunk/rtl/alttop.v