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[/] [s6soc/] [trunk/] [rtl/] [builddate.v] - Rev 54

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Rev Log message Author Age Path
51 Latest RTL changes, adding 20 cycles/instruction to CPU dgisselq 2709d 17h /s6soc/trunk/rtl/builddate.v
46 Added missing files from the 8b branch, deleted unneeded files dgisselq 2728d 17h /s6soc/trunk/rtl/builddate.v
43 Most recent build date. dgisselq 3018d 14h /s6soc/trunk/rtl/builddate.v
37 Fixed the problem with the clock running too slow. dgisselq 3025d 05h /s6soc/trunk/rtl/builddate.v
35 Minor updates and tweaks, primarily fixing the none_sel signal when the
RTC, scope, or ICAPE interface are not present.		 dgisselq 3027d 06h /s6soc/trunk/rtl/builddate.v
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.		 dgisselq 3035d 17h /s6soc/trunk/rtl/builddate.v
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.		 dgisselq 3041d 10h /s6soc/trunk/rtl/builddate.v
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.		 dgisselq 3043d 06h /s6soc/trunk/rtl/builddate.v
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.		 dgisselq 3048d 06h /s6soc/trunk/rtl/builddate.v
7 Created/added an initial specification. Updated/corrected several copywrite
notices.		 dgisselq 3048d 21h /s6soc/trunk/rtl/builddate.v
3 Updated date. dgisselq 3069d 16h /s6soc/trunk/rtl/builddate.v
2 The initial check in--all the files that will make this SoC work. dgisselq 3080d 11h /s6soc/trunk/rtl/builddate.v

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