URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [toplevel.v] - Rev 51

Rev	Log message	Author	Age	Path
51	Latest RTL changes, adding 20 cycles/instruction to CPU	dgisselq	2797d 14h	/s6soc/trunk/rtl/toplevel.v
46	Added missing files from the 8b branch, deleted unneeded files	dgisselq	2816d 14h	/s6soc/trunk/rtl/toplevel.v
31	Fixed a bug caught by Verilator.	dgisselq	3115d 03h	/s6soc/trunk/rtl/toplevel.v
13	Fixed a nasty parameter problem between toplevel and txuart. The UART transmitter now both works (again), and properly generates the required interrupts. This also finishes the fixes to the alternate toplevel file, alttop.v, that should've been fixed in the last release.	dgisselq	3129d 07h	/s6soc/trunk/rtl/toplevel.v
12	The UART and PWM audio now work. This includes the changes to make that happen, as well as the source code for some UART and PWM demo programs.	dgisselq	3130d 05h	/s6soc/trunk/rtl/toplevel.v
4	Lots of updates, as part of actually making this work on hardware. Not there yet, so this is still pre-alpha.	dgisselq	3157d 13h	/s6soc/trunk/rtl/toplevel.v
2	The initial check in--all the files that will make this SoC work.	dgisselq	3168d 08h	/s6soc/trunk/rtl/toplevel.v