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[/] [sasc/] [trunk/] [rtl/] [verilog/] [sasc_top.v] - Rev 6

Rev	Log message	Author	Age	Path
6	New directory structure.	root	5719d 22h	/sasc/trunk/rtl/verilog/sasc_top.v
5	Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug with the DPLL and data alignment: You were right that it was a problem with the dpll. I found that it was possible to get two baud clocks (rx_sio_ce) during one bit period. I fixed the problem by delaying the input data signal with a shift register and using that in the equations for the "change" variable that controls the DPLL FSM.	rudi	6796d 04h	/sasc/trunk/rtl/verilog/sasc_top.v
2	Initial Checkin	rudi	8086d 15h	/sasc/trunk/rtl/verilog/sasc_top.v