URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_ctl.v] - Rev 53

Rev	Log message	Author	Age	Path
51	FPGA relating timing optimisation done	dinesha	4657d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
50	Bug fix the request length is fixe	dinesha	4659d 07h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4666d 12h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
15	Port cleanup	dinesha	4676d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4681d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
3	SDRAM controller core files are checked in	dinesha	4687d 13h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v