URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_ctl.v] - Rev 58

Rev	Log message	Author	Age	Path
55	FPGA Synthesis timing optimisation	dinesha	4674d 13h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
54	FPGA Timing Optimisation	dinesha	4677d 10h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
51	FPGA relating timing optimisation done	dinesha	4678d 11h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
50	Bug fix the request length is fixe	dinesha	4680d 15h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4687d 20h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
15	Port cleanup	dinesha	4697d 12h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4702d 10h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
3	SDRAM controller core files are checked in	dinesha	4708d 21h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v