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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_fsm.v] - Rev 48

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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4681d 18h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4696d 08h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v

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