URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_fsm.v] - Rev 55

Rev	Log message	Author	Age	Path
55	FPGA Synthesis timing optimisation	dinesha	4668d 16h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
54	FPGA Timing Optimisation	dinesha	4671d 13h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
51	FPGA relating timing optimisation done	dinesha	4672d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
50	Bug fix the request length is fixe	dinesha	4674d 18h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4681d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4696d 13h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v