URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 20

Rev	Log message	Author	Age	Path
16	8 Bit SDRAM Support is added	dinesha	4696d 13h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
15	Port cleanup	dinesha	4699d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
13	column bit are made progrmmable	dinesha	4699d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4703d 15h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4704d 12h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
3	SDRAM controller core files are checked in	dinesha	4710d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v