URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 36

Rev	Log message	Author	Age	Path
33	clean up	dinesha	4682d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4684d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4686d 09h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
16	8 Bit SDRAM Support is added	dinesha	4688d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
15	Port cleanup	dinesha	4691d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
13	column bit are made progrmmable	dinesha	4691d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4695d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4696d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
3	SDRAM controller core files are checked in	dinesha	4702d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v