URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 36

Rev	Log message	Author	Age	Path
33	clean up	dinesha	4527d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4529d 01h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4531d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
16	8 Bit SDRAM Support is added	dinesha	4533d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
15	Port cleanup	dinesha	4536d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
13	column bit are made progrmmable	dinesha	4536d 01h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4540d 01h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4540d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
3	SDRAM controller core files are checked in	dinesha	4547d 09h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v