URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 46

Rev	Log message	Author	Age	Path
46	test bench upgrade + rtl cleanup	dinesha	4681d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4681d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4683d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4685d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
33	clean up	dinesha	4685d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4687d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4690d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
16	8 Bit SDRAM Support is added	dinesha	4691d 21h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
15	Port cleanup	dinesha	4694d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
13	column bit are made progrmmable	dinesha	4694d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4698d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4699d 20h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
3	SDRAM controller core files are checked in	dinesha	4706d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v