URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 47

Rev	Log message	Author	Age	Path
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	5175d 01h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
46	test bench upgrade + rtl cleanup	dinesha	5177d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	5177d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	5179d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5181d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
33	clean up	dinesha	5182d 01h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	5184d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	5186d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
16	8 Bit SDRAM Support is added	dinesha	5187d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
15	Port cleanup	dinesha	5190d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
13	column bit are made progrmmable	dinesha	5191d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	5195d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	5195d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v
3	SDRAM controller core files are checked in	dinesha	5202d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_core.v