URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_req_gen.v] - Rev 55

Rev	Log message	Author	Age	Path
55	FPGA Synthesis timing optimisation	dinesha	4496d 19h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
54	FPGA Timing Optimisation	dinesha	4499d 17h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
51	FPGA relating timing optimisation done	dinesha	4500d 18h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
50	Bug fix the request length is fixe	dinesha	4502d 21h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4503d 21h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
46	test bench upgrade + rtl cleanup	dinesha	4505d 21h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4506d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4510d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
33	clean up	dinesha	4510d 20h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
16	8 Bit SDRAM Support is added	dinesha	4516d 18h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
15	Port cleanup	dinesha	4519d 19h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
13	column bit are made progrmmable	dinesha	4519d 19h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
3	SDRAM controller core files are checked in	dinesha	4531d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v