URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] [sdrc_top.v] - Rev 60

Rev	Log message	Author	Age	Path
60	warning cleanup	dinesha	4671d 01h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
55	FPGA Synthesis timing optimisation	dinesha	4671d 17h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4678d 19h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
46	test bench upgrade + rtl cleanup	dinesha	4680d 19h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
38	Port Name clean up	dinesha	4684d 23h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4685d 01h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
33	clean up	dinesha	4685d 18h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4687d 17h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v