URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] [sdrc_top.v] - Rev 67

Rev	Log message	Author	Age	Path
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4375d 02h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
60	warning cleanup	dinesha	4494d 10h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
55	FPGA Synthesis timing optimisation	dinesha	4495d 02h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4502d 03h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
46	test bench upgrade + rtl cleanup	dinesha	4504d 04h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
38	Port Name clean up	dinesha	4508d 08h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4508d 09h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
33	clean up	dinesha	4509d 02h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4511d 01h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v