URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] [wb2sdrc.v] - Rev 70

Rev	Log message	Author	Age	Path
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4214d 12h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
59	Control path request and data are register now for better FPGA timing	dinesha	4651d 19h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
55	FPGA Synthesis timing optimisation	dinesha	4652d 10h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
42	Bug fix in read access is fixed	dinesha	4663d 17h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4664d 11h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4665d 18h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
33	clean up	dinesha	4666d 11h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4668d 10h	/sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v