URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr16_sim.log] - Rev 72

Rev	Log message	Author	Age	Path
65	Updated Log file with CAS latency support 4,5	dinesha	4528d 21h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
56	FPGA Synth optimisation	dinesha	4648d 13h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
53	Test bench upgradation	dinesha	4652d 11h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
48	top-level cleanup	dinesha	4655d 14h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
46	test bench upgrade + rtl cleanup	dinesha	4657d 15h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4657d 19h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4659d 17h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4659d 19h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
39	Test Bench upgradation with bigger data burst size	dinesha	4660d 14h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4661d 21h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4664d 13h	/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log