OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [model/] [mt48lc8m8a2.v] - Rev 32

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 Debug is enable through +define dinesha 4663d 23h /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v
17 micron 8 bit memory models are added into svn dinesha 4667d 22h /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.