URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [run_modelsim] - Rev 62

Rev	Log message	Author	Age	Path
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4660d 04h	/sdr_ctrl/trunk/verif/run/run_modelsim
29	SDRAM top and core related run file list are added into svn	dinesha	4664d 21h	/sdr_ctrl/trunk/verif/run/run_modelsim
5	Run files are updated into SVN	dinesha	4675d 22h	/sdr_ctrl/trunk/verif/run/run_modelsim