URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Rev 44

Rev	Log message	Author	Age	Path
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4679d 05h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4679d 07h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4684d 01h	/sdr_ctrl/trunk/verif/tb/tb_core.sv