URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 32

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4771d 23h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
25	tb.sv is renamed as tb_top	dinesha	4772d 21h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
24	Clean Up	dinesha	4772d 21h	/sdr_ctrl/trunk/verif/tb/tb.sv
22	Pad sdram clock added	dinesha	4774d 03h	/sdr_ctrl/trunk/verif/tb/tb.sv
18	8 Bit SDRAM Support is added	dinesha	4775d 21h	/sdr_ctrl/trunk/verif/tb/tb.sv
14	Unnecessary device config are removed	dinesha	4778d 22h	/sdr_ctrl/trunk/verif/tb/tb.sv
12	Column Bits are made programmable	dinesha	4778d 23h	/sdr_ctrl/trunk/verif/tb/tb.sv
8	test bench files are added into SVN	dinesha	4782d 23h	/sdr_ctrl/trunk/verif/tb/tb.sv