URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 34

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4515d 07h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
25	tb.sv is renamed as tb_top	dinesha	4516d 05h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
24	Clean Up	dinesha	4516d 05h	/sdr_ctrl/trunk/verif/tb/tb.sv
22	Pad sdram clock added	dinesha	4517d 10h	/sdr_ctrl/trunk/verif/tb/tb.sv
18	8 Bit SDRAM Support is added	dinesha	4519d 05h	/sdr_ctrl/trunk/verif/tb/tb.sv
14	Unnecessary device config are removed	dinesha	4522d 06h	/sdr_ctrl/trunk/verif/tb/tb.sv
12	Column Bits are made programmable	dinesha	4522d 06h	/sdr_ctrl/trunk/verif/tb/tb.sv
8	test bench files are added into SVN	dinesha	4526d 07h	/sdr_ctrl/trunk/verif/tb/tb.sv