OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 53

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 Test bench upgradation dinesha 4675d 15h /sdr_ctrl/trunk/verif/tb/tb_top.sv
48 top-level cleanup dinesha 4678d 18h /sdr_ctrl/trunk/verif/tb/tb_top.sv
46 test bench upgrade + rtl cleanup dinesha 4680d 19h /sdr_ctrl/trunk/verif/tb/tb_top.sv
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4680d 23h /sdr_ctrl/trunk/verif/tb/tb_top.sv
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4682d 21h /sdr_ctrl/trunk/verif/tb/tb_top.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4682d 23h /sdr_ctrl/trunk/verif/tb/tb_top.sv
39 Test Bench upgradation with bigger data burst size dinesha 4683d 18h /sdr_ctrl/trunk/verif/tb/tb_top.sv
38 Port Name clean up dinesha 4684d 23h /sdr_ctrl/trunk/verif/tb/tb_top.sv
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4685d 01h /sdr_ctrl/trunk/verif/tb/tb_top.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4687d 17h /sdr_ctrl/trunk/verif/tb/tb_top.sv
25 tb.sv is renamed as tb_top dinesha 4688d 15h /sdr_ctrl/trunk/verif/tb/tb_top.sv
24 Clean Up dinesha 4688d 15h /sdr_ctrl/trunk/verif/tb/tb.sv
22 Pad sdram clock added dinesha 4689d 21h /sdr_ctrl/trunk/verif/tb/tb.sv
18 8 Bit SDRAM Support is added dinesha 4691d 15h /sdr_ctrl/trunk/verif/tb/tb.sv
14 Unnecessary device config are removed dinesha 4694d 16h /sdr_ctrl/trunk/verif/tb/tb.sv
12 Column Bits are made programmable dinesha 4694d 17h /sdr_ctrl/trunk/verif/tb/tb.sv
8 test bench files are added into SVN dinesha 4698d 17h /sdr_ctrl/trunk/verif/tb/tb.sv

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.