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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 58

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Rev Log message Author Age Path
56 FPGA Synth optimisation dinesha 4695d 03h /sdr_ctrl/trunk/verif/tb/tb_top.sv
53 Test bench upgradation dinesha 4699d 01h /sdr_ctrl/trunk/verif/tb/tb_top.sv
48 top-level cleanup dinesha 4702d 05h /sdr_ctrl/trunk/verif/tb/tb_top.sv
46 test bench upgrade + rtl cleanup dinesha 4704d 05h /sdr_ctrl/trunk/verif/tb/tb_top.sv
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4704d 10h /sdr_ctrl/trunk/verif/tb/tb_top.sv
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4706d 08h /sdr_ctrl/trunk/verif/tb/tb_top.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4706d 09h /sdr_ctrl/trunk/verif/tb/tb_top.sv
39 Test Bench upgradation with bigger data burst size dinesha 4707d 04h /sdr_ctrl/trunk/verif/tb/tb_top.sv
38 Port Name clean up dinesha 4708d 09h /sdr_ctrl/trunk/verif/tb/tb_top.sv
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4708d 11h /sdr_ctrl/trunk/verif/tb/tb_top.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4711d 03h /sdr_ctrl/trunk/verif/tb/tb_top.sv
25 tb.sv is renamed as tb_top dinesha 4712d 02h /sdr_ctrl/trunk/verif/tb/tb_top.sv
24 Clean Up dinesha 4712d 02h /sdr_ctrl/trunk/verif/tb/tb.sv
22 Pad sdram clock added dinesha 4713d 07h /sdr_ctrl/trunk/verif/tb/tb.sv
18 8 Bit SDRAM Support is added dinesha 4715d 02h /sdr_ctrl/trunk/verif/tb/tb.sv
14 Unnecessary device config are removed dinesha 4718d 03h /sdr_ctrl/trunk/verif/tb/tb.sv
12 Column Bits are made programmable dinesha 4718d 03h /sdr_ctrl/trunk/verif/tb/tb.sv
8 test bench files are added into SVN dinesha 4722d 04h /sdr_ctrl/trunk/verif/tb/tb.sv

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