URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] [sdram_controller/] [trunk/] [sdram.vhd] - Rev 16

Rev	Log message	Author	Age	Path
16	Removed a redundant cap_en	lynn0p	5460d 02h	/sdram_controller/trunk/sdram.vhd
12	1. rolled write recover clocks back to previous value and edited comments 2. increased 200us wait time to 300us in the init module	lynn0p	5470d 02h	/sdram_controller/trunk/sdram.vhd
11	consolidated capture into one process and added comments	lynn0p	5470d 22h	/sdram_controller/trunk/sdram.vhd
10	Fixes to more glitches uncovered during testing with my T80 SoC. Some ops were getting dropped on the floor when the controller needed to do an auto refresh.	lynn0p	5471d 02h	/sdram_controller/trunk/sdram.vhd
9	Got rid of some redundant busy_n <= '0' statements	lynn0p	5472d 14h	/sdram_controller/trunk/sdram.vhd
8	Changes made to integrate and test with my homebrew SoC design. 1. One DCM has been removed. Now requires a 100mhz clock fed in. Only consumes one DCM, if you can find a 100mhz clock somewhere. 2. Small timing modifications to fix memory glitches between controller and the t80 soft cpu I'm using.	lynn0p	5472d 14h	/sdram_controller/trunk/sdram.vhd
7	Reformatted the comments so they fit in 80 columns	lynn0p	5480d 19h	/sdram_controller/trunk/sdram.vhd
6	changes to reduce synthesizer warnings, removed unused signals, etc.	lynn0p	5480d 23h	/sdram_controller/trunk/sdram.vhd
2	initial checkin	lynn0p	5481d 20h	/sdram_controller/trunk/sdram.vhd