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[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [iseconfig/] [sha256.projectmgr] - Rev 10

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10 Optimized control logic;
Reduced one clock cycle for full last blocks, eliminated sch_ld redundant logic.
Improved error detection logic, eliminating the bytes error register.
Updated testbench with write violations and full block corner case tests.		 jdoin 3008d 15h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
9 Optimized control logic;
Changed 'ack' semantics to 'data write'.
Changed error logic to detect invalid data writes.		 jdoin 3023d 12h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
8 Streamlined VHDL code to eliminate wire and combinational "initialization", changed all 'X' to 'U' on input signals, consisted comments. jdoin 3093d 17h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
7 Delete intermediate files from repository.
All commits are done after a Project/Cleanup.		 jdoin 3096d 03h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
6 Added Sim_test_1.png and Sim_test_8.png simulation pictures.
Changed testbench for faster data input.
Changed License text on all files.
Consolidated file header info.		 jdoin 3096d 03h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
4 Reduced block diagrams image sizes. jdoin 3097d 06h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
3 Added GV_SHA256 block logic schematics. jdoin 3097d 09h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
2 SHA256 RTL code simulated and verified, to all NIST verification vectors.
Pre-par synthesis show 74MHz clock rate, with no pipelining.		 jdoin 3097d 11h /sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr

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