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[/] [single_port/] [trunk/] [VHDL/] [single_port.vhd] - Rev 15

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Rev Log message Author Age Path
15 New directory structure. root 5581d 15h /single_port/trunk/VHDL/single_port.vhd
14 Address is only converted to integer when chip enable is active in order to avoid simulator warnings mgeng 6060d 11h /single_port/trunk/VHDL/single_port.vhd
13 rnw replaced by nce, nwe and noe, tristate drivers added mgeng 6788d 09h /single_port/trunk/VHDL/single_port.vhd
7 PAGENUM constant removed because the address bus width provides this information mgeng 6813d 06h /single_port/trunk/VHDL/single_port.vhd
6 Buses unconstrained, LGPL header added mgeng 6826d 04h /single_port/trunk/VHDL/single_port.vhd
2 initial checkin rpaley_yid 7828d 02h /single_port/trunk/VHDL/single_port.vhd

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