URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 135

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2945d 03h	/socgen/trunk/Makefile
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3455d 05h	/socgen/trunk/Makefile
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3498d 06h	/socgen/trunk/Makefile
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3530d 03h	/socgen/trunk/Makefile
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3633d 20h	/socgen/trunk/Makefile
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4089d 02h	/socgen/trunk/Makefile
127	final cleanup before DAC	jt_eaton	4203d 22h	/socgen/trunk/Makefile
126	added mor1kx cleanup	jt_eaton	4257d 03h	/socgen/trunk/Makefile
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4301d 21h	/socgen/trunk/Makefile
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4398d 01h	/socgen/trunk/Makefile
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4450d 20h	/socgen/trunk/Makefile
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4486d 05h	/socgen/trunk/Makefile
117	added yellow pages tools	jt_eaton	4514d 00h	/socgen/trunk/Makefile
113	started refactoring or1200	jt_eaton	4610d 17h	/socgen/trunk/Makefile
112	added more test sims removed unneeded files	jt_eaton	4620d 06h	/socgen/trunk/Makefile
106	checked in orp_soc project step 2	jt_eaton	4644d 00h	/socgen/trunk/Makefile
103	added user guide resynced to local repository	jt_eaton	4668d 21h	/socgen/trunk/Makefile
102	all ip-xact files now readable by kactus2	jt_eaton	4730d 17h	/socgen/trunk/Makefile
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4731d 18h	/socgen/trunk/Makefile
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4744d 02h	/socgen/trunk/Makefile

1 2 Next >

Show All

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 135

Filtering Options