OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 107

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 checked in orp_soc project step 2 jt_eaton 4644d 06h /socgen/trunk/Makefile
103 added user guide
resynced to local repository		 jt_eaton 4669d 04h /socgen/trunk/Makefile
102 all ip-xact files now readable by kactus2 jt_eaton 4730d 23h /socgen/trunk/Makefile
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4732d 01h /socgen/trunk/Makefile
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4744d 09h /socgen/trunk/Makefile
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4787d 01h /socgen/trunk/Makefile
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4823d 06h /socgen/trunk/Makefile
96 hierConnections now create ports jt_eaton 4897d 02h /socgen/trunk/Makefile
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4933d 02h /socgen/trunk/Makefile
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4959d 01h /socgen/trunk/Makefile
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 5056d 08h /socgen/trunk/Makefile
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 5071d 02h /socgen/trunk/Makefile
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5139d 08h /socgen/trunk/Makefile
57 Now generate all filelists from xml files jt_eaton 5172d 04h /socgen/trunk/Makefile
56 soc_builder now builds verilog from xml files jt_eaton 5177d 12h /socgen/trunk/Makefile
54 now set up fpga targets from xml files jt_eaton 5180d 10h /socgen/trunk/Makefile
53 fixed check_fpgas jt_eaton 5182d 23h /socgen/trunk/Makefile
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5183d 03h /socgen/trunk/Makefile
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5219d 12h /socgen/trunk/Makefile
28 added T6502 processor
added vga_char_ctrl		 jt_eaton 5285d 11h /socgen/trunk/Makefile

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.