URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 124

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Rev	Log message	Author	Age	Path
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4401d 23h	/socgen/trunk/Makefile
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4454d 18h	/socgen/trunk/Makefile
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4490d 03h	/socgen/trunk/Makefile
117	added yellow pages tools	jt_eaton	4517d 22h	/socgen/trunk/Makefile
113	started refactoring or1200	jt_eaton	4614d 16h	/socgen/trunk/Makefile
112	added more test sims removed unneeded files	jt_eaton	4624d 04h	/socgen/trunk/Makefile
106	checked in orp_soc project step 2	jt_eaton	4647d 22h	/socgen/trunk/Makefile
103	added user guide resynced to local repository	jt_eaton	4672d 19h	/socgen/trunk/Makefile
102	all ip-xact files now readable by kactus2	jt_eaton	4734d 15h	/socgen/trunk/Makefile
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4735d 17h	/socgen/trunk/Makefile
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4748d 00h	/socgen/trunk/Makefile
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4790d 17h	/socgen/trunk/Makefile
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4826d 22h	/socgen/trunk/Makefile
96	hierConnections now create ports	jt_eaton	4900d 18h	/socgen/trunk/Makefile
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4936d 17h	/socgen/trunk/Makefile
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4962d 17h	/socgen/trunk/Makefile
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	5060d 00h	/socgen/trunk/Makefile
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	5074d 18h	/socgen/trunk/Makefile
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5142d 23h	/socgen/trunk/Makefile
57	Now generate all filelists from xml files	jt_eaton	5175d 20h	/socgen/trunk/Makefile

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[/] [socgen/] [trunk/] [Makefile] - Rev 124

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