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[/] [socgen/] [trunk/] [Makefile] - Rev 52

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49 added covered code coverage
added xml descriptors
added soc_Link tool
jt_eaton 5189d 09h /socgen/trunk/Makefile
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v
jt_eaton 5225d 19h /socgen/trunk/Makefile
28 added T6502 processor
added vga_char_ctrl
jt_eaton 5291d 17h /socgen/trunk/Makefile
20 added Nexys2 support
expanded docs
created tools directory
jt_eaton 5324d 05h /socgen/trunk/Makefile
19 added serial_xmit module
updated and added docs
jt_eaton 5331d 11h /socgen/trunk/Makefile
16 added geda scripts and symbols/sch jt_eaton 5338d 12h /socgen/trunk/Makefile
10 added impact_bat to generate svf files jt_eaton 5368d 16h /socgen/trunk/Makefile
6 added pic_micro from minirisc project with design to run code
on a digilent Basys board
jt_eaton 5377d 13h /socgen/trunk/Makefile

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