URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 56

Rev	Log message	Author	Age	Path
56	soc_builder now builds verilog from xml files	jt_eaton	5180d 23h	/socgen/trunk/Makefile
54	now set up fpga targets from xml files	jt_eaton	5183d 20h	/socgen/trunk/Makefile
53	fixed check_fpgas	jt_eaton	5186d 09h	/socgen/trunk/Makefile
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5186d 14h	/socgen/trunk/Makefile
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5222d 23h	/socgen/trunk/Makefile
28	added T6502 processor added vga_char_ctrl	jt_eaton	5288d 21h	/socgen/trunk/Makefile
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5321d 09h	/socgen/trunk/Makefile
19	added serial_xmit module updated and added docs	jt_eaton	5328d 15h	/socgen/trunk/Makefile
16	added geda scripts and symbols/sch	jt_eaton	5335d 16h	/socgen/trunk/Makefile
10	added impact_bat to generate svf files	jt_eaton	5365d 20h	/socgen/trunk/Makefile
6	added pic_micro from minirisc project with design to run code on a digilent Basys board	jt_eaton	5374d 17h	/socgen/trunk/Makefile