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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [top.sim] - Rev 133

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133 Added Desing databases and foundation for elaborations tools jt_eaton 3479d 08h /socgen/trunk/Projects/opencores.org/Mos6502/ip/core/rtl/verilog/top.sim
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3511d 05h /socgen/trunk/Projects/opencores.org/Mos6502/ip/core/rtl/verilog/top.sim

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