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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_fpga.design.xml] - Rev 135

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135 resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0 jt_eaton 2929d 17h /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_fpga.design.xml
133 Added Desing databases and foundation for elaborations tools jt_eaton 3482d 19h /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_fpga.design.xml
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3514d 16h /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_fpga.design.xml

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