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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [testbenches/] [verilog/] [tb.ext] - Rev 134

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Rev Log message Author Age Path
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.
jt_eaton 3458d 22h /socgen/trunk/Projects/opencores.org/logic/ip/flash_memcontrl/sim/testbenches/verilog/tb.ext
133 Added Desing databases and foundation for elaborations tools jt_eaton 3501d 23h /socgen/trunk/Projects/opencores.org/logic/ip/flash_memcontrl/sim/testbenches/verilog/tb.ext
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3533d 20h /socgen/trunk/Projects/opencores.org/logic/ip/flash_memcontrl/sim/testbenches/verilog/tb.ext

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