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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body.exp5] - Rev 133

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133 Added Desing databases and foundation for elaborations tools jt_eaton 3498d 08h /socgen/trunk/Projects/opencores.org/logic/ip/micro_bus/rtl/verilog/top.body.exp5
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3530d 05h /socgen/trunk/Projects/opencores.org/logic/ip/micro_bus/rtl/verilog/top.body.exp5

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