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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [model_master.v] - Rev 135

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Rev Log message Author Age Path
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3515d 06h /socgen/trunk/Projects/opencores.org/wishbone/ip/model/rtl/verilog/sim/model_master.v

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