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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [verilog/] [top.sim] - Rev 135

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Rev Log message Author Age Path
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.
jt_eaton 3458d 19h /socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.sim
133 Added Desing databases and foundation for elaborations tools jt_eaton 3501d 20h /socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.sim
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3533d 16h /socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.sim

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